I remember doing MIPS assembler in the computer hardware class in college. We used the book "Computer Organization and Design: The Hardware/Software Interface" (aka "Patterson and Hennessy") [1]. At the time it was an enlightening experience because until then I hadn't fully internalized how computers were implemented at the hardware level.
It's interesting cause it allows you to step back and see previous machine states. Not many VM's can do this. Probably only works cause there is no OS which would clutter the set of relevant states.
I also used that book in college, it’s still sitting on my shelf. It had some really fantastic discussion of things like wait states (NOP's after branches or whatnot ) that fundamentally can't be worked around because the propagation delay of the logic gates for one operation take longer than the delay of another operation. It also talked about the dangers of long pipelines. I feel sometimes that most of the "progress" since I graduated in 1999 has been to work around these bottlenecks with things like branch prediction and excessive caching, but the cost of that has been to largely ignore more lucrative opportunities in multiprocessing.
We probably should have moved to processors with distributed CPUs/ram so that computations could be done in-place with languages like Erlang, Go and MATLAB. We should have ditched GPUs for general purpose DSPs also. Computers today really aren’t much use to me because I want to experiment with parallel code like neural nets and genetic algorithms but my hands are tied (OpenCL/CUDA focus on the wrong abstraction level). To effectively do that, I’d have to design a parallel processor with an FPGA first, say 256 MIPS cores with 4 MB of ram each at 1 GHz. As little hardware as possible would be wasted on cache and interconnect, instead, cores would just have pipes to their neighbors and software would handle replication.
Does anyone know of an open source emulator/virtual machine for a processor like this that runs on ordinary slow hardware and high latency networks? I visualize it as each core having its private memory space and the ability to open 4 sockets to its neighbors (someday 6 with 3D chips), with the global shared persistent storage showing up as a slow mount and acting as a software transactional memory for resetting and synchronizing the cores. Spinning up another instance of the VM would connect another N cores.
[1] http://www.amazon.com/Computer-Organization-Design-Fifth-Arc...